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ASAHI KASEI
[AK93C45B/55B/65B/75B]
AK93C45B / 55B / 65B / 75B
1K / 2K / 4K / 8Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION : VCC = 1.8V to 5.5V AK93C45B 1024 bits, 64 x 16 organization AK93C55B 2048 bits, 128 x 16 organization AK93C65B 4096 bits, 256 x 16 organization AK93C75B 8192 bits, 512 x 16 organization SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors LOW POWER CONSUMPTION - 0.8A Max. Standby High Reliability - Endurance : 100K cycles - Data Retention : 10 years Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE Busy/Ready status signal Software controlled write protection IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package (MSOP, SON)
DO
DATA REGISTER INSTRUCTION REGISTER
16
DI
R/W AMPS AND AUTO ERASE
16
INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION
EEPROM
93C45B=1024bit 93C55B=2048bit 93C65B=4096bit 93C75B=8192bit
ADD. BUFFERS
DECODER
CS
VPP SW
SK
PE
(AK93C55B/65B/75B)
VREF
VPP GENERATOR
Block Diagram
DAM04E-02 -12003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
General Description
The AK93C45B/55B/65B/75B is a 1024/2048/4096/8192-bit serial CMOS EEPROM divided into 64/128/256/512 registers of 16 bits each. The AK93C45B/55B/65B/75B has 4 instructions such as READ, WRITE, EWEN and EWDS. Those instructions control the AK93C45B/55B/65B/75B. The AK93C45B/55B/65B/75B can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C45B/55B/65B/75B, consisting of chip select (CS), serial clock (SK), data-in (DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C45B/55B/65B/75B takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C45B/55B/65B/75B takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output.
Software and Hardware controlled write protection When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE, EWEN and EWDS instructions. AK93C55B/65B/75B
Busy/Ready status signal After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
Type of Products Model AK93C45BH AK93C45BL AK93C55BH AK93C55BL AK93C65BH AK93C65BL AK93C75BH
DAM04E-02 -2-
Memory size 1K bits 2K bits 4K bits 8K bits
Temp. Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
VCC 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V
Package 8pin Plastic MSOP 8pin Plastic SON 8pin Plastic MSOP 8pin Plastic SON 8pin Plastic MSOP 8pin Plastic SON 8pin Plastic MSOP
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Pin Arrangement
AK93C45BH
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC NC GND
AK93C55BH/65BH/75BH
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC PE GND
8pin MSOP
8pin MSOP
AK93C45BL
VCC NC NC GND 1 2 3 4 8pin SON 8 7 6 5 CS SK DI DO
AK93C55BL/65BL
VCC NC PE GND 1 2 3 4 8pin SON 8 7 6 5 CS SK DI DO
Pin Name CS SK DI DO GND PE VCC NC
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Program Enable Power Supply Not Connected
(note) The PE is internally pulled up to VCC ( R = typ.2.5M, VCC=5V ).
DAM04E-02 -3-
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Functional Description
The AK93C45B/55B/65B/75B has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address location. The CS pin must be brought low for a minimum of 250ns (Tcs) between each instruction when the instruction is continuously executed. Instruction READ WRITE EWEN EWDS WRAL Start Op Bit Code 1 10 1 01 1 00 1 00 1 00 Address A5-A0 A5-A0 11XXXX 00XXXX 01XXXX Data D15-D0 D15-D0
Writes register. Write enable must precede all programming modes. Disables all programming instructions.
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes all registers.
X: Don't care table1. Instruction Set for the AK93C45B Instruction READ WRITE EWEN EWDS WRAL Start Op Bit Code 1 10 1 01 1 00 1 00 1 00 Address X A6-A0 X A6-A0 11XXXXXX 00XXXXXX 01XXXXXX Data D15-D0 D15-D0
Writes register. Write enable must precede all programming modes. Disables all programming instructions.
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes all registers.
X: Don't care table2. Instruction Set for the AK93C55B Instruction READ WRITE EWEN EWDS WRAL Start Op Bit Code 1 10 1 01 1 00 1 00 1 00 Address A7-A0 A7-A0 11XXXXXX 00XXXXXX 01XXXXXX Data D15-D0 D15-D0
Writes register. Write enable must precede all programming modes. Disables all programming instructions.
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes all registers.
X: Don't care table3. Instruction Set for the AK93C65B Instruction READ WRITE EWEN EWDS WRAL Start Op Address Bit Code 1 10 X A8-A0 1 01 X A8-A0 1 00 11XXXXXXXX 1 00 00XXXXXXXX 1 00 01XXXXXXXX Data D15-D0 D15-D0
Writes register. Write enable must precede all programming modes. Disables all programming instructions.
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes all registers.
X: Don't care table4. Instruction Set for the AK93C75B (Note) The WRAL instruction are used for factory function test only. User can't use the WRAL instruction. The AK93C45B/55B/65B/75B perceives the start bit in the logic"1" and also "01".
2003/05 -4-
DAM04E-02
ASAHI KASEI
[AK93C45B/55B/65B/75B]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
CS SK DI DO
0 0 1 1 0 2 1 3 4 A5 5 A4 8 A1 9 A0 10 D15 11 D14 23 D2 24 D1 25 D0 tCS
Start Bit
Op code
Hi-Z
Busy Ready tE/W
AK93C45B output a logic "1" (Ready status), if previous instruction is WRITE.
WRITE (AK93C45B)
CS SK DI DO
0 0 1 1 0 2 1 3 4 X / A7 5 A6 10 A1 11 A0 12 D15 13 D14 25 D2 26 D1 27 D0 tCS
Start Bit
Op code
Hi-Z
Busy Ready tE/W X: Don't care
AK93C55B/65B output a logic "1" (Ready status), if previous instruction is WRITE.
*Address bit A7 becomes a "don't care" for AK93C55B. WRITE (AK93C55B/65B)
CS SK DI DO
0 0 1 1 0 2 1 3 X 4 5 A8 12 A1 13 A0 14 D15 15 D14 27 D2 28 D1 29 D0 tCS
Start Bit
Op code
Hi-Z
Busy Ready tE/W X: Don't care
AK93C75B output a logic "1" (Ready status), if previous instruction is WRITE.
WRITE (AK93C75B)
DAM04E-02 -5-
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
READ
The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. When the highest address is reached, the address counter rolls over to address $00 or $000 allowing the read cycle to be continued indefinitely.
CS SK DI DO
0 0 1 1 1 2 0 3 4 A5 5 A4 8 A1 9 A0 10 11 25 26 40 41
Start bit
Op code
Hi-Z
AK93C45B output a logic "1" (Ready status), if previous instruction is WRITE.
D0 0 D15 D14 Dummy address[A5-A0] Bit
D15
D1
D0
address[A5-A0]+1
READ (AK93C45B)
CS SK DI DO
0 0 1 1 1 2 0 3 4 X / A7 5 A6 10 A1 11 A0 12 13 27 28 42 43
Start bit
Op code
Hi-Z
0 D15 D14 D0 Dummy AK93C55B/65B output a logic "1" (Ready status), address[A6/A7-A0] Bit if previous instruction is WRITE.
D15
D1
D0
address[A6/A7-A0]+1 X: Don't care
*Address bit A7 becomes a "don't care" for AK93C55B. READ (AK93C55B/65B)
CS SK DI DO
0 0 1 1 1 2 0 3 X 4 5 A8 12 A1 13 A0 14 15 29 30 44 45
Start bit
Op code
Hi-Z
AK93C75B output a logic "1" (Ready status), if previous instruction is WRITE.
0 D15 D14 D0 Dummy address[A8-A0] Bit
D15
D1
D0
address[A8-A0]+1 X: Don't care
READ (AK93C75B)
DAM04E-02 -6-
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions.
CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
Start bit
AK93C45B output a logic "1" (Ready status), if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C45B)
CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
10 X
11 X
Start bit
AK93C55B/65B output a logic "1" (Ready status), if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C55B/65B)
CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
10 X
11 X
12 X
13 X
Start bit
AK93C75B output a logic "1" (Ready status), if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C75B)
DAM04E-02 -7-
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Absolute Maximum Ratings
Parameter Power Supply All Input Voltages with Respect to Ground Ambient storage temperature Symbol VCC VIO Tst Min -0.6 -0.6 -65 Max +7.0 VCC+0.6 +150 Unit V V
C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Power Supply Ambient Operating Temperature Symbol VCC Ta Min 1.8 -40 Max 5.5 +85 Unit V C
DAM04E-02 -8-
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
AK93C45B/55B/65B
( 1.8V VCC 5.5V, -40C Ta 85C, unless otherwise specified ) Paremeter Current Dissipation (WRITE) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 Current Dissipation (Standby) Input High Voltage ICCSB VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH1 VOH2 VOH3 Output Low Voltage VOL1 VOL2 VOL3 Input Leakage Output Leakage ILI ILO Condition VCC=5.5V, tSKP=1.0s, *1 93C45B VCC=1.8V, tSKP=4s,*1 93C55B/65B VCC=5.5V, tSKP=1.0s, *1 VCC=2.5V, tSKP=2.0s, *1 VCC=1.8V, tSKP=4.0s, *1 VCC=5.5V VCC=5.0V10% 2.5V VCC 5.5V 1.8V VCC < 2.5V VCC=5.0V10% 2.5V VCC 5.5V 1.8V VCC < 2.5V VCC=5.0V10% IOH=-0.4mA 2.5V VCC 5.5V IOH=-0.1mA 1.8V VCC < 2.5V IOH=-0.1mA VCC=5.0V10% IOL=1.5mA 2.5V VCC 5.5V IOL=1.0mA 1.8V VCC < 2.5V IOL=0.1mA VCC=5.5V, VIN=5.5V VCC=5.5V, VOUT=5.5V, CS=GND *3 *2 2.0 0.8 x VCC 0.8 x VCC -0.1 -0.1 -0.1 2.2 0.8 x VCC 0.8 x VCC 0.4 0.4 0.4
1.0 1.0
Min.
Max. 4.0 1.5 2.0 0.5 0.2 0.1 0.8 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.8 0.15 x VCC 0.2 x VCC
Unit mA mA mA mA mA mA
A
Current Dissipation
(READ, EWEN, EWDS)
V V V V V V V V V V V V
A A
*1 : VIN=VIH/VIL, DO=Open *2 : VIN=VCC/GND, CS=GND, DO=Open, PE=Open(AK93C55B/65B) *3 : CS, SK, DI pin
DAM04E-02 -9-
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
AK93C75B
( 1.8V VCC 5.5V, -40C Ta 85C, unless otherwise specified ) Paremeter Current Dissipation (WRITE) Current Dissipation
(READ, EWEN, EWDS)
Symbol ICC1 ICC2 ICC3 ICC4 ICCSB VIH VIL VOH1 VOH2
Condition VCC=5.5V, tSKP=1.0s, *4 VCC=1.8V, tSKP=4.0s, *4 VCC=5.5V, tSKP=1.0s, *4 VCC=1.8V, tSKP=4.0s, *4 VCC=5.5V *5
Min.
Max. 4.0 2.0 0.4 0.1 0.8
Unit mA mA mA mA
A
Current Dissipation (Standby) Input High Voltage Input Low Voltage Output High Voltage
0.8 x VCC -0.1 2.5V VCC 5.5V IOH=-0.1mA 1.8V VCC < 2.5V IOH=-0.1mA 2.5V VCC 5.5V IOL=1.0mA 1.8V VCC < 2.5V IOL=0.1mA VCC=5.5V, VIN=5.5V VCC=5.5V, VOUT=5.5V, CS=GND *6 0.8 x VCC 0.8 x VCC
VCC + 0.5 0.2 x VCC
V V V V
Output Low Voltage
VOL1 VOL2
0.4 0.4
1.0 1.0
V V
A A
Input Leakage Output Leakage
ILI ILO
*4 : VIN=VIH/VIL, DO=Open *5 : VIN=VCC/GND, CS=GND, DO=PE=Open *6 : CS, SK, DI pin
DAM04E-02 - 10 -
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
(2) A.C. ELECTRICAL CHARACTERISTICS ( 1.8V VCC 5.5V, -40C Ta 85C, unless otherwise specified ) Paremeter SK Cycle Time Symbol tSKP1 tSKP2 tSKP3 SK Pulse Width tSKW1 tSKW2 tSKW3 CS Setup Time CS Hold Time Data Setup Time Data Hold Time Output delay *7 tCSS tCSH tDIS tDIH tPD1 tPD2 tPD3 Selftimed Programming Time Min CS Low Time CS to Status Valid CS to Output High-Z tE/W1 tE/W2 tE/W3 tCS tSV tOZ1 tOZ2 *7 : CL=100pF CL=100pF 2.0V VCC 5.5V 1.8V VCC < 2.0V 4.5V VCC 5.5V 2.0V VCC < 4.5V 1.8V VCC < 2.0V 93C45B/55B/65B 93C75B 4.5V VCC 5.5V 1.8V VCC < 4.5V 250 500 100 250 Condition 4.5V VCC 5.5V 2.0V VCC < 4.5V 1.8V VCC < 2.0V 4.5V VCC 5.5V 2.0V VCC < 4.5V 1.8V VCC < 2.0V Min. 1.0 2.0 4.0 500 1.0 2.0 100 0 200 200 500 1.0 2.0 10 8 10 Max. Unit
s s s
ns
s s
ns ns ns ns ns
s s
ms ms ms ns ns ns ns
DAM04E-02 - 11 -
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
Synchronous Data timing
CS
tCSS tSKW tSKW tSKP
SK
tDIS tDIH
DI
tSV
0
1
DO
Hi-Z
AK93C45B/55B/65B/75B output a logical "1" (Ready status), if previous instruction is WRITE.
The Start of Instruction
CS
tCSH
SK DI
tPD tPD tPD tOZ
DO
D3
D2
D1
D0
Hi-Z
The End of Instruction
DAM04E-02 - 12 -
2003/05
ASAHI KASEI
[AK93C45B/55B/65B/75B]
tCS
CS
tCSH
SK
tDIS tDIH
DI DO
D1
D0
tSV Hi-Z Busy tE/W Ready
Busy/Ready Signal Output
DAM04E-02 - 13 -
2003/05
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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